The present invention relates to memory systems for random access memories and, more particularly, to memory systems based on bipolar transistors.
Digital memories of various kinds are used extensively in computers and computer system components, digital processing systems, and the like. This increasing use has been made possible primarily by the rapid shrinking in size of monolithic integrated circuits that has been occurring in recent years. Such shrinkage has allowed an increase in the density of circuits provided in monolithic integrated circuit chips, and this has both improved performance and reduced cost.
Memory cell circuits based on bipolar transistors have been used primarily because of the speed of operation which can be obtained with such transistors. However, the advent of merged complementary bipolar transistor structures has permitted fabricating bipolar transistor memories also having a substantial density of memory cells in a monolithic integrated circuit chip.
A typical merged transistor circuit for a memory cell has a pair of PNP bipolar transistors serving as loads, and has a further pair of cross-coupled NPN bipolar transistors serving as the control transistors for operating the memory cell circuit. The emitters of the PNP bipolar transistors are connected to a memory system word line interconnection extending from the address decoding circuitry, and the emitters of the NPN bipolar transistors are connected to a corresponding memory system standby line interconnection also extending from the same decoding circuitry. Each control transistor has its collector connected to the other's base and to both the base of one PNP load transistor and to the collector of the other PNP load transistor.
In those situations in which the memory cell is not about to have information stored therein or to have information retrieved therefrom, the cell is in the standby mode of operation and relatively lower voltages are applied to both the word line and the standby line to which such a cell is connected. An increase in the voltages of these two interconnection lines occurs selectively, occurring in response to an appropriate address being presented to the memory indicating through the decoding circuitry the row of memory cells in which the cell of interest is located. This increase in voltage will permit storing or retrieving information from this memory cell.
The two bit lines associated with this cell are typically connected through a switching device of a suitable kind to the collectors, or to second emitters, of each control transistor. The arrangement is configured in the memory cell through these bit lines or retrieving information therefrom over these bit lines when there has been an increase in the voltage on the word line and the standby line to which the memory cell is connected as the basis for selecting that cell for such an operation.
In operation, one of the control NPN bipolar transistors is in the "on" condition, as is its corresponding PNP bipolar load transistor. Current thus flows through the memory cell bistable circuit side having these two devices by flowing in these devices, but not through the other side of the memory cell, to thereby set the state of that cell and so the information which it contains. The state of the cell is set by the combination of alternative voltage values occurring at the collectors of the control transistors or the alternative combinations of current flows through the sides of the memory cell.
Such a memory cell has a drawback, however, because the two transistors are in the "on" condition, and as a result, each is operated so as to be well into the saturation region thereof. This results in the storage of charge carriers in each of the base regions thereof, and so the switching time of such a pair of transistors from the "on" condition to the "off" condition is slowed. Such a slowing of the switching means that information cannot be stored in the memory cell as quickly as it might otherwise be, thus slowing the operation of the memory. Slowing the operation of the memory, in turn, slows the operation of the system in which the memory is used.
One improvement that can be made in such a memory cell is to have each of the PNP load transistors therein provided with a second collector connected to its base. This in effect provides current from both the base and the collector of that PNP load transistor which is in the "on" condition to the collector of the corresponding NPN control transistor rather than from just the base of such a PNP load transistor. This arrangement then reduces the base current required from that PNP load transistor, and correspondingly limits the saturation thereof. Such a PNP bipolar transistor then draws less base current therethrough. There is also less current flowing out of the other collector of the PNP transistor into the base of its control transistor to thereby reduce its saturation.
A further possibility is to provide a pair of supplemental NPN transistors having the emitters thereof connected to the collectors of the control transistors and the collectors thereof connected to the memory system word line. The bases of the supplemental transistors are connected to the bases of the control transistors. Such a supplemental transistor on the "on" condition side of the memory cell will provide a shunting of current around the PNP load transistor to supply the demand for current at the collector of the NPN control transistor. This will limit the current which needs to be provided through the base of the PNP load transistor to keep it from being driven far into saturation. This also will lead to supplying a smaller collector current from the PNP load transistor to the NPN control transistor to keep that transistor from being driven far into saturation, enabling both to switch into the "off" condition faster during a subsequent storing operation in the memory cell.
Even with these improvements in the memory cell design of the type using complementary load and control bipolar transistors, there are inherent system limitations which slow the operation of the memory system. Effectively selecting one row of memory cells by increasing the word line voltage and the standby interconnection line voltage involved with respect to similar interconnection lines for the other rows requires that the word line voltage be more than 1.0 volt above the voltage of the word lines of the other rows. This is to assure that the storing of information in a memory cell in that row does not affect the memory cells connected to the same bit lines in another row. Once such a word line is established at this higher voltage, the selection of another row requires discharging the capacitance of the word line in the previously selected row to decrease the relatively large voltage placed thereon for its selection. This leads to substantial current in that row as its selection is being terminated.
Each row has a word line with a total effective capacitance comprising the distributed capacitance associated with the row word line itself, the standby line, and the junction capacitances associated with the electronic components in the cells. The discharge of such a capacitance in terminating the selection of a row, by changing the voltage on the row word line back to its standby value, should occur as rapidly as possible. This is because satisfactory memory operation forbids having more than one row of memory cells selected simultaneously beyond a transient switching period. Such simultaneous selection could occur by having a relatively high voltage on both the word line being newly selected and the one for which selection is being ceased. Such rapid discharges lead to relatively large memory cell currents which results in increasing the effect of diffusion capacitances in the cell thus further slowing the operation.
Supplying such large currents typically requires a substantial current supply capability for the word line decoding circuitry, and is usually further aided by the provision of a word line discharge circuit for each row. The word line structure to carry the large required currents adds capacitance to the word lines and, with such large signal changes thereon, tends to slow retrieval of information from the memory cell.
Also, storing information in such a memory cell requires changes in bit line voltages on the order of one-half volt (0.5 v) requiring further capacitive charges and discharges and slows operation. Providing for sufficient decoder current supply capability and the relatively large bit line voltage changes further requires providing a separate current source for each bit line rather than being able to switch bit lines between a single source.
In addition, digital systems using such memories have increasingly required memories which have the ability to store information in two different memory cells in each storage cycle, or to store information in one cell and retrieve it from another cell in a single cycle, or other similar combinations. Such dual port, or multi-port, memories have often been implemented by lengthening the data storage time period or the data retrieval time period to permit two such operations to occur sequentially during such periods so that it appears that there have been two operations done in each memory operation cycle. Such lengthening of memory operation cycles, of course, slows the operation of the memory insofar as storing or retrieving from any one cell.
Thus, there is a desire to have a memory system which operates with reduced current flow through the memory cells therein to increase the rapidity of operation of that system. Further, there is a desire to have a memory system which permits multiple simultaneous storage and retrieval operations without reducing the rapidity of operation of the memory system with respect to any one such operation.